EDN

Reducing switching power with intelligent clock gating

Clock gating is a well-understood power optimization technique employed in both ASIC and FPGA designs to eliminate unnecessary switching activity. This method usually requires that the designers add a ...
Electronic Design

1.5-GHz FPGA Takes Clock Gating To The Max

Flexibility is key to FPGA success, but speed is equally important. Achronix almost triples the throughput of the system by taking clock gating to the extreme. The Achronix Speedster FPGAs use a ...
EDN

Analysis of Power Savings from Intelligent Clock Gating

This application note introduces FPGA designers to intelligent clock gating by describing clock gating support in the Xilinx design tools while supplying a detailed analysis of the impact of clock ...
Design-Reuse

Xilinx ISE Design Suite 12 Enables Up to 30% Dynamic Power Reduction with Intelligent Clock-Gating Technology

AMBA 4 AXI4 IP Support and Innovations in Design Preservation Combined with ISE Power Optimization to Deliver New Levels of Productivity for Virtex-6 and Spartan-6 FPGAs SAN JOSE, Calif., May 3, 2010- ...
Electronic Design

FPGA Design Tool Brings More Modularity To FPGA Design

Xilinx's latest incarnation of its Integrated Synthesis Environment, ISE Design Suite 12, now brings features such as ‘intelligent’ clock-gating technology to its line of FPGAs as well as a new ...
Design-Reuse

Xilinx ISE Design Suite 12.3 Introduces AMBA 4 AXI4 IP Cores, Enhances PlanAhead Design and Analysis Cockpit, Extends Power Optimization

Release of ISE Design Suite 12.3 Begins Roll-Out of IP Supporting AXI4 interfaces for Plug-and-Play FPGA Design SAN JOSE, Calif., Oct 05, 2010 --Xilinx, Inc. (Nasdaq: XLNX) today announced the release ...