First collaboration milestone speeds validation of IP and design correlation on UMC's 14-nm FinFET process Process qualification vehicle validates key process and IP test structures Tapeout helps ...
Multi-year agreement drives alignment of next-generation processor, physical IP, and process technology foruse in high-performance, energy-efficient mobile and enterprise markets Hsinchu, Taiwan and ...
IC Compiler II and Design Compiler Graphical provide a complete digital implementation flow delivering optimized power, performance, area, and full via pillar support StarRC, PrimeTime, NanoTime, and ...
Samsung Electronics is introducing a third 14-nano FinFET system semiconductor process that has lower electricity consumption and production cost than previous cost. According to the Electronic Times, ...
Customers adopting Design Compiler NXT report significant reduction in runtimes together with improvements in power, performance and area (PPA) New advanced optimizations, such as concurrent clock and ...
And that's good news for AMD folks. Samsung announced that it has begun mass production of advanced logic chips utilizing its 14 nm LPP (Low-Power Plus) process, the 2nd generation of the company's 14 ...
GLOBALFOUNDRIES recently announced their upcoming 7nm FinFET manufacturing process which is expected to go into production in early 2018. According to the GLOBALFOUNDRIES, their new 7nm FinFET ...
Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced certification and immediate ...
Mentor, a Siemens business, today announced that several tools in its Calibre™ nmPlatform and Analog FastSPICE (AFS™) Platform have been certified on TSMC's 5nm FinFET process technology. Mentor also ...
SAN FRANCISCO -- Jun 02, 2014 -- Stating that not all FinFETs are created equal, Samsung Electronics Co., Ltd., a global leader in advanced semiconductor solutions, today announced that the IP and ...
ARM and TSMC announced a multi-year agreement to collaborate on a 7nm FinFET process technology which includes a design solution for future low-power, high-performance compute SoCs. The agreement ...
Sidense, the Ottawa developer of NV OTP IP cores, says it has demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated on TSMC’s 16nm CMOS finfet process.
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