EDN

Achieving completeness in IP functional verification

This article formalizes the concept of best possible verification quality — completeness — and describes a methodology, field-proven on many complex module and intellectual property (IP) designs, that ...
EDN

Verification a challenging part of IP reuse

The industry is looking to intellectual-property (IP) reuse as way to deal with the complexity of today's interfaces and to meet time-to-market goals. Deciding to use IP in a design is a brave first ...
Semiconductor Engineering

Bridging IP With Verification Standards

Standards body Accellera is sounding the gong to summon all verification IP providers to check out its efforts in connection with IP-XACT — IEEE 1685, “Standard for IP-XACT, Standard Structure for ...
Electronic Design

11 Myths About Verification IP

It’s time to put to rest 11 of the most common myths about verification intellectual property (VIP). SmartDV’s Bipul Talukdar, Director of Applications Engineering, explains why it’s used in a ...
Nasdaq

Cadence Announces First-to-Market NVMe 1.4 Verification IP for High-Performance Computing

Cadence VIP with TripleCheck reduces time to market and supports the next-generation NVMe standard SAN JOSE, Calif.--(BUSINESS WIRE)-- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the ...
Semiconductor Engineering

Next Steps In Verification IP

With the cost of failure at an astronomical high, the last thing chip designers want to worry about is the physical IP they will use to build their SoC. In addition to less willingness on the customer ...
Business Wire

Cadence Brings Verification IP to the Chip Level with New System VIP Solution

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced Cadence ® System-Level Verification IP (System VIP), a new suite of tools and libraries for automating ...
Embedded

Synopsys enables multi-die designs with HBM3 IP and verification

Synopsys has launched what it said is the industry’s first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers ...
Business Wire

PLDA Announces a Unique CXL™ Verification IP Ecosystem, Delivering Robust Verification That Reduces Time-to-Design for CXL 2.0 Applications

SAN JOSE, Calif.--(BUSINESS WIRE)--PLDA, the industry leader in high-speed interconnect solutions, today announced their CXL™ Verification IP Ecosystem which includes IP from partners Truechip and ...
Electronic Design

Assertion-Based Verification Smoothes The Road To IP Reuse

Theoretically, the use—and subsequent reuse—of intellectual property (IP) should ease the pain of verification. IP lets designers break up the project into self-contained functional blocks, each of ...
Nasdaq

Synopsys Announces Industry's First JEDEC DDR5 Verification IP for Next-Generation DRAM/DIMM Designs

MOUNTAIN VIEW, Calif., July 14, 2020 /PRNewswire/ -- Synopsys, Inc. (Nasdaq: SNPS) today announced the availability of the industry's first JEDEC DDR5 (JESD79-5) compliant Verification IP (VIP) for ...