IEEE

DRAM Technology & Design Optimization for Sub-10nm and Beyond

Abstract: Over the past 25 years, as design rule decreased by 90%, the DRAM cell capacitance also decreased by 90%. Despite those reductions, advances in cell transistors, optimizations of sensing ...
IEEE

A Multi-WL Approach to Suppress Gate-Induced Drain Leakage, Floating Body Effect, and Row Hammer Effect in Array Transistor of 4F2 DRAM and 3D Stackable DRAM

Abstract: Targeting the next-generation 4F2 DRAM and 3D stackable DRAM, we propose a multi-wordline (preferably 2-wordline) array transistor for 1T1C DRAM to efficiently minimize gate-induced drain ...