May 28, 2025 · There is a RFsock4x2 board I need to use shown below,I need to run 4 signals from DAC depending on the gpio interrupt being raised. I am new to vivado and vitis , I am …

Jul 6, 2025 · Hello , I started to build a block diagram for my xczu48dr-ffvg1517-2-e component in vivado the proccesor called zynq ulatascale+MPSoC. When I try to do the...

Mar 28, 2013 · Hello, I simulated correctly my system with a RTL simulation, now I'm trying to simulate the system with a post-syntehsis timing simulation in Vivado 2018.3. I correctly …

Aug 2, 2012 · how to make synthesizable 8.86 Mhz clock in vhdl? in test bench it can be easily made but i need to use it on fpga i am able to make 10 MHZ but can i make accurate 8.86 MHz??

Oct 24, 2014 · The tools then attempt to met the published timing numbers in the device based on the constraints you provided. I think you need to read UG945 (Vivado Design Suite Tutorial: …

Jul 26, 2019 · Hello, I have created my own IP in Vivado which takes some data from a sensor using I2C protocol and stores them in the memory mapped registers in the processing system …

Feb 21, 2014 · At 50 MHz this will make timing on any part in that Vivado can implement without multicycle constraints (which is what the OP observed). Try implementing a 64-bit * 64-bit (C = …

Jun 21, 2016 · Vivado Simulation compiler has the following two commands (scripts) xvlog and xvhdl to compile the different languages. I believe these are scripts that call the same base …

Nov 9, 2021 · 185 Hello, I am to create a connection between AXI UART16550 and RS-422. I am to use the IP from the Xilinx library but am having a hard time configuring it to do as I want. …

Aug 14, 2013 · DO I have to set additionally something in synthesis tool/vivado to say use DSP block and not LUTs? or I must have to instantiate DSP48E2 and configured accordingly, if I …